TPS54873

SLVS444 – OCTOBER 2002

www.ti.com

2

Thesedevices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

TA

OUTPUT VOLTAGE

PACKAGE

PART NUMBER

– 40

°C to 85°C

0.9 V to 3.3 V

Plastic HTSSOP (PWP)(1)

TPS54873PWP

(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54873PWPR). See the application section of

the data sheet for PowerPAD drawing and layout information.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

TPS54873

VIN, SS/ENA, SYNC

–0.3 V to 7 V

Input voltage range V

RT

–0.3 V to 6 V

Input voltage range, VI

VSENSE

–0.3 V to 4V

BOOT

–0.3 V to 17 V

Output voltage range V

VBIAS, COMP, PWRGD

–0.3 V to 7 V

Output voltage range, VO

PH

–0.6 V to 10 V

Source current I

PH

Internallylimited

Source current, IO

COMP, VBIAS

6 mA

PH

12 A

Sink current, IS

COMP

6 mA

Sink current, IS

SS/ENA, PWRGD

10 mA

Voltage differential

AGND to PGND

±0.3 V

Operating virtual junction temperature range, TJ

–40

°C to 125°C

Storage temperature, Tstg

–65

°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

300

°C

(1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX

UNIT

Input voltage, VI

4

6

V

Operating junction temperature, TJ

–40

125

°C

PACKAGE

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

TA =25°C

POWER RATING

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

28 Pin PWP with solder

18.2

°C/W

5.49 W(3)

3.02 W

2.20 W

28 Pin PWP without solder

40.5

°C/W

2.48 W

1.36 W

0.99 W

(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.

(2) Test board conditions:

1. 3” x 3”, 4 layers, thickness: 0.062”

2. 1.5 oz. copper traces located on the top of the PCB

3. 1.5 oz. copper ground plane on the bottom of the PCB

4. 0.5 oz. copper ground planes on the 2 internal layers

5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)

(3) Maximum power dissipation may be limited by over current protection.