HT45F0060 datasheet(12/95 Pages) HOLTEK

12 / 95 page

Rev. 1.00

July 19, 2017

Rev. 1.00

July 19, 2017

HT45F0060

RGB Dimming LED Flash MCU

HT45F0060

RGB Dimming LED Flash MCU

System Architecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed

totheirinternalsystemarchitecture.Thedevicetakesadvantageoftheusualfeaturesfoundwithin

RISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.The

pipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecution

areoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranch

orcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,which

carriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,

etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.

CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyorindirectly

addressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditionalarchitectural

featuresensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/O

controlsystemwithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost,

high-volumeproductionforcontrollerapplications.

Clocking and Pipelining

Themainsystemclock,derivedfromeitheraHIRCorLIRCoscillatorissubdividedintofour

internallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthe

beginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4

clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleforms

oneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive

instructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsare

effectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructionswherethe

contentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasethe

instructionwilltakeonemoreinstructioncycletoexecute.

Fetch Inst. (PC+2)

Execute Inst. (PC+1)

Oscillator Clock

(System Clock)

Phase Clock T1

Phase Clock T2

Phase Clock T3

Phase Clock T4

Program Counter

Pipelining

PC+1

PC+2

Fetch Inst. (PC+1)

Execute Inst. (PC)

Execute Inst. (PC-1)

Fetch Inst. (PC)

System Clocking and Pipelining

Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twomachinecyclesare

requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone

cycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe

branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming

sensitiveapplications.

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