VITESSE

SEMICONDUCTOR CORPORATION

G52293-0, Rev 2.3

Page 1

05/07/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Advance Product Information

VSC7124

Quad Port Bypass Circuit

Features

General Description

The VSC7124 contains five cascaded Port Bypass Circuits (PBCs) used to steer serial signals. This part is typ-

ically used in distributing Fibre Channel signals to an array of disk drives in an FC-AL loop as illustrated in Fig-

ure 1. The VSC7124 can be used with any of the Vitesse JBOD circuits to implement FC-AL JBODs of

virtually any size. In Figure 1, the first VSC7127’s CRU is configured as a Repeater to attenuate jitter. The

VSC7124 does not contain a CRU in order to reduce power and cost. The second VSC7127’s CRU is config-

ured as a retimer so that the output of the device is a jitter compliance point.

Each PBC is a multiplexer that is controlled by the corresponding SELx line which, if HIGH, selects the exter-

nal input or, if LOW, selects the output of the previous PBC.

VSC7124 Block Diagram

• ANSI X3T11 Fibre Channel Compliant at 1.0625Gb/s

• IEEE 802.3z Gigabit Ethernet Compliant at 1.25Gb/s

• Five Port Bypass Circuits (PBCs)

• On-Chip Transmit Termination

• 3.3V, 0.25W Typical Power

• 0.35um CMOS, a Velocity Family Member

• 44-Pin, 10mm PQFP Package

1

0

PBC1

1

0

PBC2

1

0

PBC3

1

0

PBC4

1

0

PBC0