SLG46534 datasheet(92/172 Pages) DIALOG

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SLG46534_DS_107

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SLG46534

Each cell also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. The 50 mV and 200 mV hysteresis

options can be used with internal voltage reference only, while 25 mV hysteresis option can be used with both internal and external

voltage reference. The 50 mV and 200 mV hysteresis options are one way hysteresis. It means that the actual thresholds will be

Vref (high threshold) and Vref - hysteresis (low threshold). The ACMP output will retain its previous value, if the input voltage is

within threshold window (between Vref and Vref - hysteresis). Please note: for the 25 mV hysteresis option threshold levels will

be Vref + hysteresis/2 (high threshold) and Vref – hysteresis/2 (low threshold).

Note: Any ACMP powered on enables the BandGap internal circuit as well. An analog voltage will appear on Vref even when the

Force BandGap option is set as Disabled.

For high input impedance when using the gain divider (x0.25, x0.33, x0.5), it is possible to use the input buffer. However, this will

add some offset, see Figure 53. It is not recommended to use ACMP buffer when VDD < 2.5 V.

Table 73. Gain Divider Input Resistance

Gain

x0.5

x0.33

x0.25

Input Resistance

100 MΩ

1 MΩ

0.75 MΩ

1 MΩ

Table 74. Gain Divider Accuracy

Gain

x0.5

x0.33

x0.25

Accuracy

±0.51%

±0.34%

±0.25%

Figure 53. Typical Buffer Input Voltage Offset vs. Voltage Reference at T = (-40.... +85)°C,

Buffer Bandwidth = 1 kHz, Vhys = 0 mV, Gain = 1.

-40

-30

-20

-10

250

600

850

1200

VOLTAGE REFERENCE (mV)

Upper Limit @ VDD≥2.7V

Lower Limit @ VDD≥2.7V

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