SLG46200 datasheet(13/69 Pages) DIALOG

13 / 69 page

000-0046200-124

Page 8 of 64

SLG46200

6.0 Summary of Macro Cell Function

6.1 I/O Pins (6 total)

•

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)

•

Open Drain

•Push-Pull

•

Analog I/O

•

50k

Ω/100kΩ/300kΩ pull-up/pull-down resistors

6.2 Connection Matrix

•

Digital matrix for circuit connections based on user design

6.3 Delays/Counters (CNT/DLY 3 total)

•0.5

μs to 380ms (4.5s for DLY1) delay time range

•

Three 14-bit counters (one Finite State Machine counter)

6.4 Analog to Digital Converter (ADC)

•

8-bit, up to 7.5kHz, Successive Approximation Register ADC

•

DNL < ±1LSB, INL < ±2LSB

•VIN Range: 0 ~ 1.7V

•

Common Mode Voltage Range: VPP/2 ~ VDD/2

•

3-bit Programmable Gain Amplifier with gain values of (1, 2, 4, 8,16X in differential mode and 0.5, 1, 2, 4, 8X in single-ended

mode)

•

SPI output format

6.5 Analog Comparators (ACMP 2 total)

•

50mV Hysteresis

6.6 Pulse Width Modulator (PWM)

•8-bit

•

Clock Frequency 43kHz - 7.8MHz, with dead band control

6.7 Digital Comparators (DCMP 2 total)

•8-bit

•

Clock Frequency 43kHz - 7.8MHz

6.8 Serial-to-Parallel / Parallel-to-Serial Converter (S2P)

•

Serial-to-Parallel

•

Parallel-to-Serial

•

SPI Format

6.9 Combinatorial Logic LUTs (7 total)

•

Used to create either standard or custom digital logic functions

•

Two 2-bit Lookup Tables

•

Four 3-bit Lookup Tables

•

One 4-bit Lookup Tables

6.10 Logic Storage Devices (DFFs/LATCHes 3 total)

•

D Flip-Flops or Latches

SLG46200 датащи(PDF) 13 Page - Dialog Semiconductor

SLG46200 датащи(HTML) 13 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

датащи скачать

ссылки URL