ST34C87

2

Rev. 1.01

PIN CONFIGURATION

16 Lead PDIP (0.300”)

INPUT D

OUTPUT D+

OUTPUT D-

ENABLE C/D

OUTPUT C-

OUTPUT C+

INPUT C

INPUT A

OUTPUT A+

OUTPUT A-

ENABLE A/B

OUTPUT B-

OUTPUT B+

INPUT B

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

16 Lead SOIC (Jedec, 0.150”)

16

1

9

8

2

3

4

5

6

7

15

14

13

12

11

10

INPUT D

OUTPUT D+

OUTPUT D-

OUTPUT C-

OUTPUT C+

INPUT C

INPUT A

OUTPUT A+

OUTPUT A-

OUTPUT B-

OUTPUT B+

INPUT B

GND

ENABLE C/D

ENABLE A/B

PIN DESCRIPTION

Pin #

Symbol

Type

Description

1

INPUT A

I

Driver A input pin.

2

OUTPUT

A+

O

Driver A differential non-inverting output pin.

3

OUTPUT

A-

O

Driver A differential inverting output pin.

4

ENABLE

A/B

I

Gate control (active high). This pin is one of the two control pins which enables or disables all

four drivers. All four drivers are gated with two input or gate.

5

OUTPUT

B-

O

Driver B differential inverting output pin.

6

OUTPUT

B+

O

Driver B differential non-inverting output pin.

7

INPUT B

I

Driver B input pin.

8

GND

O

Signal and power ground.

9

INPUT C

I

Driver C input pin.

10

OUTPUT

C+

O

Driver C differential non-inverting output pin.

11

OUTPUT

C-

O

Driver C differential inverting output pin.

12

ENABLE

C/D

I

Gate control (active low). See ENABLE A/B pin description.

13

OUTPUT

D-

O

Driver D differential inverting output pin.

14

OUTPUT

D+

O

Driver D differential non-inverting output pin.

15

INPUT D

I

Driver D input pin.

16

I

Power supply pin.