DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.0

07-Apr-2017

CFR0011-120-00

3 of 54

© 2017 Dialog Semiconductor

11.5.1

Input Under-Voltage............................................................................................. 32

11.5.2

Over-Temperature ............................................................................................... 33

11.5.3

PVC Current Limit................................................................................................ 33

11.5.4

PVC Start-Up Failure ........................................................................................... 33

11.6 VCORE Voltage Regulator ................................................................................................. 33

11.7 VDDIO Generation .............................................................................................................. 33

11.8 Internal Oscillator ................................................................................................................ 34

11.8.1

Internal Temperature Supervision ....................................................................... 34

12 Control Interface.......................................................................................................................... 35

12.1 I

2C Communication ............................................................................................................. 35

12.2 I

2C Control Bus Protocol ..................................................................................................... 35

13 Register Definitions .................................................................................................................... 38

14 Package Information ................................................................................................................... 50

14.1 Package Outline.................................................................................................................. 50

14.2 Suggested PCB Layout....................................................................................................... 51

14.3 RouteEasyTM Technology Chart ........................................................................................ 51

15 Application Information .............................................................................................................. 52

15.1 Recommended Capacitors ................................................................................................. 52

16 Ordering Information .................................................................................................................. 52

Revision History ................................................................................................................................ 53

Figures

Figure 1: Functional Block Diagram Standalone (I

2C Not Connected) ................................................. 6

Figure 2: Functional Block Diagram Master/Slave Operation (I

2C Not Connected).............................. 7

Figure 3: Functional Block Diagram Standalone (I

2C Connected) ........................................................ 8

Figure 4: Functional Block Diagram Master/Slave Operation (I

2C Connected) .................................... 9

Figure 5: Connection Diagram ............................................................................................................ 10

Figure 6: I

2C Bus Timing ..................................................................................................................... 18

Figure 7: DA9313 Efficiency Automatic Mode Standalone ................................................................. 19

Figure 8: DA9313 Efficiency Fixed Frequency Mode Standalone....................................................... 19

Figure 9: DA9313 Output Voltage Drop Automatic Mode Standalone ................................................ 20

Figure 10: DA9313 Efficiency Automatic Mode Master/Slave............................................................. 20

Figure 11: DA9313 Efficiency Fixed Frequency Mode Master/Slave.................................................. 21

Figure 12: DA9313 Output Voltage Drop Automatic Mode Master/Slave ........................................... 21

Figure 13: Master Slave Timing in Automatic Frequency Mode ......................................................... 28

Figure 14: Operating Modes................................................................................................................ 30

Figure 15: Timing of I

2C START and STOP Condition........................................................................ 36

Figure 16: I

2C Byte Write (SDA Line) .................................................................................................. 36

Figure 17: I

2C Byte Read (SDA Line) .................................................................................................. 36

Figure 18: I

2C Page Read (SDA Line)................................................................................................. 37

Figure 19: I

2C Page Write (SDA Line) ................................................................................................. 37

Figure 20: I

2C Repeated Write (SDA Line).......................................................................................... 37

Figure 21: 43 WLCSP Package Outline Drawing................................................................................ 50

Figure 22: Suggested PCB Layout ...................................................................................................... 51