FDMF5833 datasheet(13/25 Pages) ONSEMI

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Power Sequence

SPS FDMF5833 requires four (4) input signals to

conduct normal switching operation: VIN, VCC / PVCC,

PWM, and EN. PWM should not be applied before VCC

and the amplitude of PWM should not be higher than

VCC. All other combinations of their power sequences

are allowed. The below example of a power sequence

is for a reference application design:

! From no input signals

-> VIN On: Typical 12 VDC

-> VCC / PVCC On: Typical 5 VDC

-> EN HIGH: Typical 5 VDC

-> PWM Signaling: 5 V HIGH / 0 V LOW

The VIN pins are tied to the system main DC power rail.

PVCC and VCC pins are tied together to supply gate

driving and logic circuit powers from the system VCC

rail. Or the PVCC pin can be directly tied to the system

VCC rail, and the VCC pin is powered by PVCC pin

through a filter resistor located between PVCC pin and

VCC pin. The filter resistor reduces switching noise

impact from PVCC to VCC.

The EN pin can be tied to the VCC rail with an external

pull-up resistor and it will maintain HIGH once the VCC

rail turns on. Or the EN pin can be directly tied to the

PWM controller for other purposes.

High-Side Driver

The high-side driver (HDRV) is designed to drive a

floating N-channel MOSFET (Q1). The bias voltage for

the high-side driver is developed by a bootstrap supply

circuit, consisting of the internal Schottky diode and

external bootstrap capacitor (CBOOT). During startup, the

SW node is held at PGND, allowing CBOOT to charge to

PVCC through the internal bootstrap diode. When the

PWM input goes HIGH, HDRV begins to charge the

gate of the high-side MOSFET (internal GH pin). During

this transition, the charge is removed from the CBOOT

and delivered to the gate of Q1. As Q1 turns on, SW

rises to VIN, forcing the BOOT pin to VIN + VBOOT, which

provides sufficient VGS enhancement for Q1. To

complete the switching cycle, Q1 is turned off by pulling

HDRV to SW. CBOOT is then recharged to PVCC when

the SW falls to PGND. HDRV output is in phase with

the PWM input. The high-side gate is held LOW when

the driver is disabled or the PWM signal is held within

the 3-state window for longer than the 3-state hold-off

time, tD_HOLD-OFF.

Low-Side Driver

The low-side driver (LDRV) is designed to drive the

gate-source of a ground-referenced, low-RDS(ON),

N-channel MOSFET (Q2). The bias for LDRV is

internally connected between the PVCC and AGND.

When the driver is enabled, the driver output is 180° out

of phase with the PWM input. When the driver is

disabled (EN = 0 V), LDRV is held LOW.

Continuous Current Mode 2 (CCM2) Operation

A main feature of the low-side driver design in SPS

FMDF5833 is the ability to control the part of the low-

side gate driver upon detection of negative inductor

current,

called

CCM2

operation.

This

accomplished by using the ZCD comparator signal.

The primary reason for scaling back on the drive

strength is to limit the peak VDS stress when the low-

side MOSFET hard-switches inductor current. This

peak VDS stress has been an issue with applications

with large amounts of load transient and fast and

wide output voltage regulation.

The MOSFET gate driver in SPS FDMF5833 operates

in one of three modes, described below.

Continuous Current Mode 1 (CCM1) with Positive

Inductor Current

In this mode, inductor current is always flowing towards

the output capacitor, typical of a heavily loaded power

stage. The high-side MOSFET turns on with the low-

side body diode conducting inductor current and SW is

approximately VF below ground, meaning hard-

switched turn on and off the high-side MOSFET.

Discontinuous Current Mode (DCM)

Typical of lightly loaded power stage; the high-side

MOSFET turns on with zero inductor current, ramps the

inductor current, then returns to zero every switching

cycle. When the high-side MOSFET turns on under

DCM operation, the SW node may be at any voltage

from a VF below ground to a VF above VIN. This is

because after the low-side MOSFET turns off, the SW

node capacitance resonates with the inductor current.

The level shifter in driver IC should be able to turn on

the high-side MOSFET regardless of the SW node

voltage. In this case, the high-side MOSFET turns off a

positive current.

During this mode, both LDRV1 and LDRV2 operate in

parallel and the low-side gate driver pull-up and pull-

down resistors are operating at full strength.

Continuous Current Mode 2 (CCM2) with Negative

Inductor Current

This mode is typical in a synchronous buck converter

pulling energy from the output capacitors and delivering

the energy to the input capacitors (Boost Mode). In this

mode, the inductor current is negative (meaning

towards the MOSFETs) when the low-side MOSFET is

turned off (may be negative when the high-side

MOSFET turns on as well). This situation causes the

low-side MOSFET to hard switch while the high-side

MOSFET acts as a synchronous rectifier (temporarily

operated in synchronous Boost Mode).

During this mode, only the “weak” LDRV2 is used for

low-side MOSFET turn-on and turn-off. The intention is

to slow down the low-side MOSFET switching speed

when it is hard switching to reduce peak VDS stress.

Dead-Times in CCM1 / DCM / CCM2

The driver IC design ensures minimum MOSFET dead

times, while eliminating potential shoot-through (cross-

conduction) currents. To ensure optimal module

efficiency, body diode conduction times must be

reduced to the low nano-second range during CCM1

and DCM operation. CCM2 alters the gate drive

impedance while operating the power MOSFETs in a

different mode versus CCM1 / DCM. Altered dead-time

operation must be considered.

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