Philips Semiconductors

Product specification

GTL16612

universal translator (3-State)

2

2002 Dec 13

FEATURES

LVTTL/TTL logic levels (A ports)

(A ports); +40 mA on the GTL/GTL+ side (B ports)

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

DESCRIPTION

The GTL16612 is a high-performance BiCMOS product designed for

This device is an 18-bit universal transceiver featuring non-inverting

3-State bus compatible outputs in both send and receive directions.

Data flow in each direction is controlled by output enable (OEAB and

OEBA), latch enable (LEAB and LEBA), and clock (CPAB and

CPBA) inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is High. When LEAB is Low, the A

data is latched if CPAB is held at a High or Low logic level. If LEAB

is Low, the A-bus data is stored in the latch/flip-flop on the

Low-to-High transition of CPAB. When OEAB is Low, the outputs are

active. When OEAB is High, the outputs are in the high-impedance

state. The clocks can be controlled with the clock-enable inputs

(CEBA/CEAB).

Data flow for B-to-A is similar to that of A-to-B but uses OEBA,

LEBA and CPBA.

QUICK REFERENCE DATA

CONDITIONS

TYPICAL

SYMBOL

PARAMETER

CONDITIONS

3.3 V

UNIT

Propagation delay

An to Bn or Bn to An

1.9

ns

Input capacitance (Control pins)

4

pF

I/O pin capacitance

8

pF

Total supply current

Outputs disabled

12

mA

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DWG NUMBER

56-Pin Plastic SSOP

-40 to +85

°C

GTL16612DL

SOT371-1

56-Pin Plastic TSSOP

-40 to +85

°C

GTL16612DGG

SOT364-1

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.