AD9671EBZ datasheet(47/61 Pages) AD

47 / 61 page

AD9671

Data Sheet

Rev. A| Page 46 of 60

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the chip

configuration register map (Address 0x000 to Address 0x19C), the

profile register map (Address 0xF00 to Address 0xFFF), and the

coefficient register map (Address 0x1000 to Address 0x1FFF).

Registers that are designated as local registers use the device

index in Address 0x004 and Address 0x005 to determine to

which channels of a device the command is applied. Registers

that are designated as chip registers use the chip address mode

in Address 0x115 to determine whether the device is to be

updated by writing to the chip register.

The first column of the memory map indicates the register address,

and the default value is shown in the second rightmost column.

The Bit 7 (MSB) column is the start of the default hexadecimal

value given. For example, Address 0x011, the LNA and VGA gain

adjustment register, has a default value of 0x06, meaning that

Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 1, Bit 1 =

1, and Bit 0 = 0, or 0000 0110 in binary. This setting is the default

for GAIN± pins enabled, PGA gain = 24 dB and LNA gain =

21.6 dB.

For more information about the SPI memory map and other

functions, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

RESERVED LOCATIONS

Do not write to undefined memory locations except when

writing the default values suggested in this data sheet. Addresses

that have values marked as 0 must be considered reserved and

have a 0 written into their registers during power-up.

DEFAULT VALUES

After a reset, critical registers are automatically loaded with default

values. These values are indicated in Table 33, where an X refers

to an undefined feature (don’t care).

LOGIC LEVELS

An explanation of various registers follows: “bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “bit is cleared” is synonymous with “bit is set

to Logic 0” or “writing Logic 0 for the bit.”

RECOMMENDED START-UP SEQUENCE

To save system power during programming, the AD9671 powers

up in power-down mode. To start the device up and initialize

the data interface, the SPI commands listed in Table 32 are

recommended. At a minimum, write the profile memory for an

index of 0 (Address 0xF00 to Address 0xF07; see Table 27). If

additional profiles and coefficient memory are required, write these

after Profile File Memory 0.

Table 32. AD9671 SPI Write Start-Up Sequence Example

Address

Value

Description

0x000

0x3C

Initiate SPI reset

0x002

0x0X (default)

Set speed mode to 40 MSPS

0x0FF

0x01

Enable speed mode change

0x004

0x0F

Set local registers to all channels

0x005

0x3F

Set local registers to all channels

0x113

0x03

Bypass demodulator and decimator, bypass RF decimator, enable high pass filter

0x011

0x06 (default)

Set LNA gain= 21.6 dB, GAIN± pins enabled, and PGA gain = 24 dB

0xF00

0xFF

Continuous run mode enable; do not power down channels (POWER_STOP LSB)

0xF01

0x7F

Continuous run mode enable; do not power down channels (POWER_STOP MSB)

0xF02

0x00

Power up all channels 0 clock cycles after TX_TRIG± signal assertion (POWER_START LSB)

0xF03

0x80

Digital high-pass bypassed (POWER_START MSB)

0xF04

0x0C

Decimate by 2 (M = 00001); digital gain = 16 (g = 100)

0xF05

0x00

Point to Coefficient Block 00

0xF06

0x00

demodulation frequency = fSAMPLE/8

0xF07

0x20

demodulation frequency = fSAMPLE/8

0x10C1

0x00 (default)

Set index profile (required after profile memory writes)

0x014

0x00

Set output data format

0x008

0x00

Chip run (TGC mode)2

0x021

0x12

16-bit, four-lane mode

0x199

0x80

Enables automatic serializer/deserializer (SERDES) sample clock counter

0x142

0x04

ILAS enabled

0x188

0x01

Enable start code identifier

0x18B

0x27

Set START_CODE MSB

0x18C

0x72

Set START_CODE LSB

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