TLF12486

April 1996

DS90CF581DS90CF582

LVDS 24-Bit Color Flat Panel Display (FPD) Link

General Description

The DS90CF581 transmitter converts 28 bits of CMOSTTL

data into four LVDS (Low Voltage Differential Signaling)

data streams A phase-locked transmit clock is transmitted

in parallel with the data streams over a fifth LVDS link Every

cycle of the transmit clock 28 bits of input data are sampled

and transmitted The DS90CF582 receiver converts the

LVDS data streams back into 28 bits of CMOSTTL data At

a transmit clock frequency of 40 MHz 24 bits of RGB data

and 4 bits of LCD timing and control data (FPLINE

FPFRAME DRDY CNTL) are transmitted at a rate of

280 Mbps per LVDS data channel Using a 40 MHz clock

the data throughput is 140 Megabytes per second The

chipset is an ideal means to solve EMI and cable size prob-

lems associated with wide high speed TTL interfaces

Features

Y

Up to 140 Megabytesec Bandwidth

Y

Narrow bus reduces cable size

Y

345 mV swing LVDS devices for low EMI

Y

Low power CMOS design

Y

Power-down mode

Y

PLL requires no external components

Y

Low profile 56-lead TSSOP package

Y

Falling edge data strobe

Y

Compatible with TIAEIA-644 LVDS standard

Block Diagrams

DS90CF581

DS90CF582

TLF12486 – 1

Order Number DS90CF581MTD

See NS Package Number MTD56

Order Number DS90CF582MTD

See NS Package Number MTD56

Application

TLF12486 – 2

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1996 National Semiconductor Corporation

RRD-B30M66Printed in U S A