MAX77816 datasheet(13/26 Pages) MAXIM

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Slave Address

I2C slave address of the IC is shown in Table 3.

Clock Stretching

In general, the clock signal generation for the I2C bus is

the responsibility of the master device. I2C specification

allows slow slave devices to alter the clock signal by

holding down the clock line. The process in which a slave

device holds down the clock line is typically called clock

stretching. The IC does not use any form of clock stretch-

ing to hold down the clock line.

General Call Address

The IC does not implement I2C specification called

general call address. If the IC sees general call address

(00000000b), it will not issue an ACKNOWLEDGE (A).

Communication Speed

The IC provides I2C 3.0-compatible (3.4MHz) serial inter-

face.

● 0Hz to 100kHz (standard mode)

● 0Hz to 400kHz (fast mode)

● 0Hz to 1MHz (fast mode plus)

Operating in standard mode, fast mode, and fast mode

plus does not require any special protocols. The main

consideration when changing the bus speed through this

range is the combination of the bus capacitance and pul-

lup resistors. Higher time constants created by the bus

capacitance and pullup resistance (C x R) slow the bus

operation. Therefore, when increasing bus speeds, the

pullup resistance must be decreased to maintain a rea-

sonable time constant. Refer to the Pullup Resistor Sizing

section of I2C revision 3.0 specification for detailed guid-

ance on the pullup resistor selection. In general, for bus

capacitances of 200pF, a 100kHz bus needs 5.6kΩ pul-

lup resistors, a 400kHz bus needs about a 1.5kΩ pullup

resistors, and a 1MHz bus needs 680Ω pullup resistors.

Note that the pullup resistor is dissipating power when the

open-drain bus is low. The lower the value of the pullup

resistor, the higher the power dissipation (V2/R).

At power-up and after each STOP condition, the IC inputs

filters are set for standard mode, fast mode, or fast mode

plus (i.e. 0Hz to 1MHz).

Communication Protocols

The IC supports both writing and reading from its regis-

ters. The following sections show the I2C communication

protocols for each functional block. The power block uses

the same communications protocols.

Writing to a Single Register

Figure 10 shows the protocol for I2C master device to

write one byte of data to the IC. This protocol is the same

as SMBus specification’s write byte protocol.

The write byte protocol is as follows:

1) The master sends a START command (S).

2) The master sends the 7-bit slave address followed by

a write bit (R/nW = 0).

3) The addressed slave asserts an ACKNOWLEDGE

(A) by pulling SDA low.

4) The master sends an 8-bit register pointer.

5) The slave acknowledges the register pointer.

6) The master sends a data byte.

7) The slave acknowledges the data byte. At the rising

edge of SCL, the data byte will be loaded into its tar-

get register and the data will become active.

8) The master sends a STOP condition (P) or a

REPEATED START condition (Sr). Issuing a P

ensures that the bus input filters are set for 1MHz or

slower operation. Issuing a REPEATED START (Sr)

leaves the bus input filters in their current state.

Figure 9. Slave Address Byte Example

Table 3. I2C Slave Address

SLAVE ADDRESS (7 bit)

SLAVE ADDRESS (Write)

SLAVE ADDRESS (Read)

001 1000 (7’h18)

0x30 (0011 0000)

0x31 (0011 0001)

SCL

SDA

ACKNOWLEDGE

R/W

MAX77816

High-Efficiency Buck-Boost Regulator

with 5A Switches

www.maximintegrated.com

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