ADAS1000-4BSTZ datasheet(17/80 Pages) AD

17 / 80 page

Data Sheet

ADAS1000-3/ADAS1000-4

Rev. B | Page 17 of 80

ADAS1000-3 Pin No.

ADAS1000-4 Pin No.

Mnemonic

Description

LQFP

LFCSP

LQFP

LFCSP

SCLK

Clock Input. Data is clocked into the shift register on a rising edge and clocked out on a

falling edge.

SDI

Serial Data Input.

PDE

Power-Down, Active Low.

SDO

Serial Data Output. This pin is used for reading back register configuration data and for

the data frames.

DRDYE

Digital Output. This pin indicates that conversion data is ready to be read back when

low, busy when high. When reading packet data, the entire packet must be read to

allow

DRDYE

to return high.

RESETE

Digital Input. This pin has an internal pull-up resistor. This pin resets all internal nodes to

their power-on reset values.

SYNC_GANG

Digital Input/Output (Output on Master, Input on Slave). Used for synchronization

control where multiple devices are connected together. Powers up in high impedance.

GPIO0/

MCSE

General-Purpose I/O or Master 128 kHz SPI

CSE

GPIO1/MSCLK

General-Purpose I/O or Master 128 kHz SPI SCLK.

GPIO2/MSDO

General-Purpose I/O or Master 128 kHz SPI SDO.

GPIO3

General-Purpose I/O.

1, 3, 4, 5,

6, 13, 14,

16, 17,

32, 33,

48, 49,

62, 64

2, 3, 10,

11, 12,

13, 16

1, 13, 14,

16, 17, 32,

33, 48, 49,

2, 3

No connect. Do not connect to these pins (see Figure 7, Figure 8, Figure 9, and

Figure 10).

EPAD

Exposed Pad. The exposed pad is on the top of the package; it is connected to the most

negative potential, AGND.

ADAS1000-4BSTZ датащи(PDF) 17 Page - Analog Devices

ADAS1000-4BSTZ датащи(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL