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IIS2DH датащи(PDF) 43 Page - STMicroelectronics

номер детали IIS2DH
подробное описание детали  Ultra-low-power high-performance 3-axis accelerometer with digital output for industrial applications
PDF  49 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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IIS2DH
Register description
49
Interrupt 2 source register. Read-only register.
Reading at this address clears the INT2_SRC (35h) IA bit (and the interrupt signal on the
INT2 pin) and allows the refresh of data in the INT2_SRC (35h) register if the latched option
was chosen.
7.25
INT2_THS (36h)
7.26
INT2_DURATION (37h)
The D[6:0] bits set the minimum duration of the Interrupt 2 event to be recognized. Duration
time steps and maximum values depend on the ODR chosen.
7.27
CLICK_CFG (38h)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Table 64. INT2_SRC description (continued)
Table 65. INT2_THS register
0
THS6
THS5
THS4
THS3
THS2
THS1
THS0
Table 66. INT2_THS description
THS[6:0]
Interrupt 2 threshold. Default value: 000 0000
1 LSb = 16 mg @ FS = 2 g
1 LSb = 32 mg @ FS = 4 g
1 LSb = 62 mg @ FS = 8 g
1 LSb = 186 mg @ FS = 16 g
Table 67. INT2_DURATION register
0
D6D5D4D3D2D1D0
Table 68. INT2_DURATION description
D[6:0]
Duration value. Default value: 000 0000
1 LSb = 1/ODR(1)
1. Duration time is measured in N/ODR, where N is the content of the duration register.
Table 69. CLICK_CFG register
--
--
ZD
ZS
YD
YS
XD
XS



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