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LTC5100EUF датащи(PDF) 46 Page - Linear Technology |
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LTC5100EUF датащи(HTML) 46 Page - Linear Technology |
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46 / 52 page ![]() LTC5100 46 sn5100 5100fs Table 29. Register: IM_DAC—Modulation Current DAC (I2C Command Code 0x02) REGISTER RESET VALUE .BITFIELD BIT (BIN) FUNCTION AND VALUES .Reserved 15:10 .Im_dac 9 0 DAC Setting for the Peak-to-Peak Modulation Current (the Combined MODA and MODB Pin Currents) 8 0 Read Access to This DAC is Always Available. Write Access is Only Valid if LPC_en = 0. 70 60 50 40 30 20 10 00 REGISTER DEFI ITIO S Table 30. Register: PWR_LIMIT_DAC—Optical Power Limit DAC—Read Only (I2C Command Code 0x03) REGISTER RESET VALUE .BITFIELD BIT (BIN) FUNCTION AND VALUES .Reserved 15:7 .pwr_limit_dac 6 0 DAC Setting for the Over and Underpower Fault Detection Comparator (Read Only) Read Only 5 0 This Bit Field Has Different Functions Depending on Apc_en. 40 Constant Current Control (CCC) Mode (Apc_en = 0): Pwr_limit_dac Has No Function in This Mode. 30 Its Contents are Undefined. 20 Automatic Power Control (APC) Mode (Apc_en = 1): Pwr_limit_dac Tracks the Value of the Monitor 10 Diode Current. The Laser Power Controller Continuously Updates the PWR_LIMIT_DAC with the 00 Most Recent ADC Reading of Imd. Reading the DAC Will Return the Value of Imd_adc Shifted Right by Three Bits. I= Im_dac 1024 M •(Im_ )• ( ) rng mA typical + 19 |
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