LTC5100 datasheet(33/52 Pages) LINER

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LTC5100

sn5100 5100fs

OPERATIO

Table 6. Effective Base Addresses for Various Sized EEPROMs

GENERIC PART NUMBER

24LC00

24LC01B

24LC02B

24LC04B

24LC16B

Bits

128

16k

Bytes

128

256

512

2048

Device Address (Binary)

1010xxx.

1010.xxa

1010cba.

Word Address Space (Binary)

xxxx_nnnn

xnnn_nnnn

nnnn_nnnn

LTC5100 Generates

1010_111.

Device Address

= 0xAE

LTC5100 Generates

0110_0000

Word Address

= 0x60

Effective Base Address

0000_0000

0110_0000

0001_0110_0000

0111_0110_0000

= 0x00

= 0x60

= 0x160

= 0x760

Comments

Minimum Size

EEPROM Not Big

Standard GBIC

LTC5100 Loads

EEPROM.

Enough for GBIC

EEPROM.

from an Area

Loads Every

ID. LTC5100

Smallest EEPROM

Outside the GBIC

Byte in the

Loads from 0x60

That is Big Enough

ID Data Area

EEPROM.

to 0x6F

to Hold the LTC5100

Data and the GBIC ID.

LTC5100 Loads from

0x60 to 0x6F, the First

16 Bytes of the

Vendor Area

Microprocessor Controlled Operation

An external microprocessor or a test computer can take

full control of the LTC5100 by setting the Operating_mode

bit. When this bit is set, the LTC5100 stops searching for

an external EEPROM and takes commands from the mi-

croprocessor. It is even possible to combine standalone

and microprocessor controlled modes. If an EEPROM is

present, the LTC5100 will load its configuration registers

from the EEPROM at power-up. A microprocessor or test

computer can then read and write the LTC5100 registers

at will.

The primary purpose of the Operating_mode bit is to stop

the LTC5100’s EEPROM load attempts. Once the LTC5100

has loaded itself from an EEPROM (if present), it is not

technically necessary to set the Operating_mode bit to

communicate with the LTC5100.

The LTC5100 attempts to read the EEPROM every 64ms

until it successfully loads its registers or until the

Operating_mode bit is set. There is a finite chance that the

microprocessor and the LTC5100 will generate an I2C bus

collision if an EEPROM load attempt coincides with the

microprocessor’s attempt to access the LTC5100. In this

case, the microprocessor will receive a NACK (not-ac-

knowledged) response to its transmissions. The micro-

processor needs only to cease transmission in accordance

with the I2C protocol and try again. If the microprocessor

makes this second attempt within 64ms (typical), it is

guaranteed not to collide with the LTC5100.

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