REV. E

AD7701

–5–

PIN FUNCTION DESCRIPTIONS

Pin No.

PDIP,

CERDIP,

SOIC

SSOP

Mnemonic Description

11

MODE

Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in

the Asynchronous Communications (AC) mode. The SCLK pin is configured as an

input, and data is transmitted in two bytes, each with one start bit and two stop bits. If

MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected.

SCLK is configured as an input, and the output appears without formatting, the MSB

coming first. If MODE is tied to +5 V, the AD7701 operates in the Synchronous

Self-Clocking (SSC) mode. SCLK is configured as an output, with a clock frequency of

22

CLKOUT

Clock Output to Generate an Internal Master Clock by Connecting a Crystal between

CLKOUT and CLKIN. If an external clock is used, CLKOUT is not connected.

33

CLKIN

Clock Input for External Clock.

4, 17

4, 25

SC1, SC2

System Calibration Pins. The state of these pins, when CAL is taken high, determines

the type of calibration performed.

55

DGND

Digital Ground. Ground reference for all digital signals.

68

Digital Negative Supply, –5 V Nominal.

6, 7, 9, 11,

NC

No Connect.

18, 21, 22, 23

710

Analog Negative Supply, –5 V Nominal.

812

AGND

Analog Ground. Ground reference for all analog signals.

913

Analog Input.

10

14

Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale

in the Unipolar mode and of both positive and negative full scale in Bipolar mode.

11

15

SLEEP

Sleep Mode Pin. When this pin is taken low, the AD7701 goes into a low power mode

with typically 10

µW power consumption.

12

16

BP/

UP

Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a uni-

configured for a bipolar input range,

13

17

CAL

Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7701

is reset and performs a calibration cycle when CAL is brought low again. The CAL pin

can also be used as a strobe to synchronize the operation of several AD7701s.

14

19

Analog Positive Supply, +5 V Nominal.

15

20

Digital Positive Supply, +5 V Nominal.

16

24

CS

Chip Select Input. When

CS is brought low, the AD7701 will begin to transmit serial

data in a format determined by the state of the MODE pin.

18

26

DRDY

Data Ready Output.

DRDY is low when valid data is available in the output register. It

goes high after transmission of a word is completed. It also goes high for four clock

cycles when a new data-word is being loaded into the output register, to indicate that

valid data is not available, irrespective of whether data transmission is complete or not.

19

27

SCLK

Serial Clock Input/Output. The SCLK pin is configured as an input or output, depen-

dent on the type of serial data transmission that has been selected by the MODE pin.

When configured as an output in the Synchronous Self-Clocking mode, it has a fre-

20

28

SDATA

Serial Data Output. The AD7701’s output data is available at this pin as a 16-bit serial

word. The transmission format is determined by the state of the MODE pin.