TPS60310 datasheet(17/20 Pages) TI

17 / 20 page

TPS60310, TPS60311, TPS60312, TPS60313

SINGLE-CELL TO 3-V/3.3-V, 20-mA DUAL OUTPUT,

HIGH-EFFICIENCY CHARGE PUMP WITH SNOOZE MODE

SLVS362A – MAY 2001 – REVISED AUGUST 2001

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

output filter design (continued)

OUT1

C(OUT1)

µF

OUT2

C(OUT2)

µF

VIN

CIN

µF

SNOOZE

GND

TPS60312

C2F

µF

C2+

C2–

C1+

C1–

C1F

µF

CPG

0.1

µF

1.5 V

MSP430

Display

Amplifier

Sensor

1 M

Figure 25. Application With MSP430; PG as Supply for Analog Circuits

power dissipation

As given in the data sheet, the thermal resistance of the unsoldered package is RθJA = 294°C/W. Soldered on

the EVM, a typical thermal resistance of RθJA(EVM) = 200°C/W was measured.

The thermal resistance can be calculated using equation 4.

RθJA +

J–TA

(4)

Where:

TJ is the junction temperature.

TA is the ambient temperature.

PD is the power that needs to be dissipated by the device.

The maximum power dissipation can be calculated using equation 5.

PD = VIN × IIN – VO × IO = VIN(max) × (3 × IO + I(SUPPLY)) – VO × IO

(5)

The maximum power dissipation happens with maximum input voltage and maximum output current:

At maximum load the supply current is approximately 2 mA.

PD = 1.8 V × (3 × 20 mA + 2 mA) – 3.3 V × 20 mA = 46 mW

(6)

With this maximum rating and the thermal resistance of the device on the EVM, the maximum temperature rise

above ambient temperature can be calculated using equation 7.

∆TJ = RθJA × PD = 200°C/W × 46 mW = 10°C

(7)

This means that internal dissipation increases TJ by 10°C.

The junction temperature of the device must not exceed 125

°C.

This means the IC can easily be used at ambient temperatures up to:

TA = TJ(max) – ∆TJ = 125°C – 10°C = 115°C

(8)

layout and board space

All capacitors should be soldered as close as possible to the IC. A PCB layout proposal for a two-layer board

is shown in Figure 26. Care has been taken to connect all capacitors as close as possible to the circuit to achieve

optimized output voltage ripple performance. The bottom layer is not shown in Figure 26. It only consists of a

ground-plane with a single track between the two vias that can be seen in the left part of the top layer.

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