SLG46826 datasheet(2/165 Pages) DIALOG

2 / 165 page

Datasheet

31-Jan-2018

CFR0011-120-01

Revision 2.4

2 of 165

SLG46826

GreenPAK Programmable Mixed Signal Matrix with In-System

Programmability

PRELIMINARY

Contents

1 Block Diagram ......................................................................................................................................................................7

2 Pinout ....................................................................................................................................................................................8

2.1 Pin Configuration - STQFN- 20L ............................................................................................................................8

2.2 Pin Configuration - TSSOP-20L .............................................................................................................................9

3 Characteristics ...................................................................................................................................................................13

3.1 Absolute Maximum Ratings .................................................................................................................................13

3.2 Recommended Operating Conditions .................................................................................................................13

3.3 Electrical Characteristics ......................................................................................................................................13

3.4 Timing Characteristics .........................................................................................................................................17

3.5 OSC Characteristics .............................................................................................................................................19

3.6 ACMP Specifications ............................................................................................................................................21

3.7 Analog Temperature sensor (ts) specifications ....................................................................................................24

4 User Programmability ........................................................................................................................................................26

5 IO Pins .................................................................................................................................................................................27

5.1 IO Pins .................................................................................................................................................................27

5.2 GPIO Pins ............................................................................................................................................................27

5.3 GPO Pins .............................................................................................................................................................27

5.4 GPI Pins ...............................................................................................................................................................27

5.5 Pull Up/Down Resistors .......................................................................................................................................27

5.6 Fast Pull-up/down during Power up .....................................................................................................................27

5.7 I2C Mode IO Structure (VDD or VDD2) ...............................................................................................................28

5.8 Matrix OE IO Structure (VDD or VDD2) ...............................................................................................................29

5.9 Register OE IO Structure (VDD or VDD2) ...........................................................................................................30

5.10 Register OE IO Structure (VDD or VDD2) .........................................................................................................31

6 Connection Matrix ..............................................................................................................................................................32

6.1 Matrix Input Table ................................................................................................................................................33

6.2 Matrix Output Table .............................................................................................................................................34

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................37

6.4 Connection Matrix Virtual Outputs .......................................................................................................................38

7 Combination Function Macrocells ....................................................................................................................................39

7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................39

7.4 3-Bit LUT or Pipe Delay / Ripple Counter Macrocell ............................................................................................52

8 Multi-Function Macrocells .................................................................................................................................................57

8.1 3-Bit LUT or 8- Bit Counter / Delay Macrocells ....................................................................................................57

8.2 CNT/DLY/FSM Timing Diagrams .........................................................................................................................66

8.3 4-Bit LUT or 16-Bit Counter / Delay Macrocell .....................................................................................................74

8.4 WAKE AND SLEEP CONTROLLER ....................................................................................................................76

9 Analog Comparators ..........................................................................................................................................................80

9.1 ACMP0H Block Diagram .....................................................................................................................................81

9.2 ACMP1H Block Diagram .....................................................................................................................................82

9.3 ACMP2L Block Diagram .....................................................................................................................................83

9.4 ACMP3L Block Diagram .....................................................................................................................................84

10 Programmable Delay / Edge Detector ............................................................................................................................85

10.1 Programmable Delay Timing Diagram - Edge Detector Output .........................................................................85

11 Additional Logic Function. Deglitch Filter .....................................................................................................................86

12 Voltage Reference (VREF) ...............................................................................................................................................87

12.1 Voltage Reference Overview .............................................................................................................................87

12.2 VREF Selection Table .......................................................................................................................................87

12.3 VREF Block Diagram ........................................................................................................................................88

13 Clocking ............................................................................................................................................................................89

13.1 Oscillator0 (2.048 kHz) .......................................................................................................................................90

13.2 Oscillator1 (2.048 MHz) .....................................................................................................................................91

13.3 Oscillator2 (25 MHz) ..........................................................................................................................................92

13.4 Clock Scheme ...................................................................................................................................................93

13.5 External Clocking ...............................................................................................................................................93

14 Power On Reset (POR) .....................................................................................................................................................94

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