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HAL700 датащи(PDF) 5 Page - Micronas |
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HAL700 датащи(HTML) 5 Page - Micronas |
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5 / 12 page ![]() ADVANCE INFORMATION HAL700 Micronas 5 2. Functional Description The HAL 700 is a monolithic integrated circuit with two independent subblocks consisting each of a Hall plate and the corresponding comparator. Each subblock independently switches the comparator output in response to the magnetic field at the location of the corresponding sensitive area. If a magnetic field with flux lines perpendicular to the sensitive area is present, the biased Hall plate generates a Hall voltage proportional to this field. The Hall voltage is compared with the actual threshold level in the comparator. The subblocks are designed to have closely matched switching points. The output of comparator 1 attached to S1 controls the open drain output at Pin 3. Pin 2 is set according to the state of comparator 2 connected to S2. The temperature-dependent bias – common to both subblocks – increases the supply voltage of the Hall plates and adjusts the switching points to the decreas- ing induction of magnets at higher temperatures. If the magnetic field exceeds the threshold levels, the com- parator switches to the appropriate state. The built-in hysteresis prevents oscillations of the outputs. In order to achieve good matching of the switching points of both subblocks, the magnetic offset caused by mechanical stress is compensated for by use of “switching offset compensation techniques”. Therefore, an internal oscillator provides a two-phase clock to both subblocks. For each subblock, the Hall voltage is sampled at the end of the first phase. At the end of the second phase, both sampled and actual Hall voltages are averaged and compared with the actual switching point. Shunt protection devices clamp voltage peaks at the Output-pins and VDD-pin together with external series resistors. Reverse current is limited at the VDD-pin by an internal series resistor up to −15 V. No external reverse protection diode is needed at the VDD-pin for reverse voltages ranging from 0 V to −15 V. Fig. 2–1: Timing diagram Fig. 2–2: HAL 700 block diagram t Clock t BS1 t BS2 t Pin 2 t Pin 3 t IDD BS1on BS2on VOH VOL VOH VOL 1/fosc tf tf Reverse Voltage and Overvoltage Protection Temperature Dependent Bias Hysteresis Control Hall Plate 1 Switch Comparator GND 4 1 VDD Hall Plate 2 Switch Comparator Clock Output 3 S1-Output Output 2 S2-Output Short Circuit and Overvoltage Protection S1 S2 |
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