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SAMA5D2 датащи(PDF) 39 Page - ATMEL Corporation

номер детали SAMA5D2
подробное описание детали  SAMA5D2 Xplained Ultra Evaluation Kit
PDF  74 Pages
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производитель  ATMEL [ATMEL Corporation]
домашняя страница  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

SAMA5D2 датащи(HTML) 39 Page - ATMEL Corporation

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SAMA5D2 Xplained Ultra [USER GUIDE]
Atmel-44028C-ATARM-SAMA5D2-Xplained-Ultra-User Guide_13-Oct-16
39
Figure 5-38.
JTAG J11
R18
R11
R24
C3
C2
C9
R10
R23
TP1 TP2
J1
R27
C11
R25
BP1
C12
L2
J2
R26
C13
L3
C14
L4
C18
C16
R48
R45
R47
JP2
R30
R41
C17
R46
C15
R43
C21
R64
R61
R60
R49
C25
R44
C19
R59
JP4
C33
C26
C39
R71
R62
C32
R123
R105
R100
R75
R103
R104
R99
R130
C44
R131 L12
JP6
C46
C47
R102
R101
7
9
R8
9
R
R152
R146
C51
R143
R142
R141
R140
R139
C48
R128
R127
R126
R125
R107
R106
C50
C49
L13
J15
R154
R151
R150
R149
R148
R147
R145
R144
R153
R158
R155
R163
R161
R159
R156
R160
R157
BP2
C53
R169
R167
R165
R177
R175
R173
R171
R172
R170
R168
R166
JP7
C56
BP3
R176
R174
R184
R183
C57
4
2
3
4
2
3
4
1
3
4
2
3
2
D22
D23
V
5V
5
BOOT_DIS
WWW.ATMEL.COM
D51
D49
D50
D48
A5-JTAG
EDBG-JTAG
D47
D46
D45
D43
D44
D42
VDDBU
D41
D40
D39
D37
D38
D36
HSIC
D35
D33
D34
D32
D31
D30
D29
D27
D28
D26
VDDIODDR
D25
D24
D53
GND
GND
D52
R
VDD_3V3
CLASS D
TM
VDDCORE
RTS GND
RXD VCC
TXD
CTS
EDBG_DIS
DEBUG
PB_USER
DEBUG_DIS
LCD
VBAT
Table 5-14.
JTAG/ICE Connector J11 Signal Descriptions
Pin
Mnemonic
Signal Description
1
VTref. 3.3V power
This is the target reference voltage (main 3.3V).
2
TMS TEST MODE SELECT
JTAG mode set input into target CPU
3
GND
Common ground
4
TCK TEST CLOCK - Output timing signal, for
synchronizing test logic and control register access
JTAG clock signal into target CPU
5
GND
Common ground
6
TDO JTAG TEST DATA OUTPUT - Serial data
input from the target
JTAG data output from target CPU
7
RTCK - Input Return test clock signal from the
target
Some targets having too slow system clock must synchronize the JTAG
inputs to internal clocks. In present case such synchronization is
unneeded and TCK merely looped back into RTCK.
8
TDI TEST DATA INPUT - Serial data output line,
sampled on the rising edge of the TCK signal
JTAG data input into target CPU
9
GND
Common ground
10
nSRST RESET
Active-low reset signal. Target CPU reset signal.



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