CY29972
Document #: 38-07290 Rev. *A
Page 6 of 8
Maximum Ratings [5]
Maximum input voltage relative to VSS: .............. VSS – 0.3V
Maximum input voltage relative to VDD:............... VDD + 0.3V
Storage temperature: .............................–65 × C to +150 × C
Operating temperature:............................–40 × C to +85 × C
Maximum ESD protection ................................................ 2kV
Maximum power supply: .................................................5.5V
Maximum input current: .............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
VSS < (VIN or VOUT) < VDD .
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
VSS
–
0.8
V
VIH
Input High Voltage
2.0
–
VDD
V
IIL
Input Low Current[6]
––120
µA
IIH
Input High Current
10
µA
VOL
Output Low Voltage[7]
IOL = 20mA
0.5
V
VOH
Output High Voltage[7]
IOH = –20mA
2.4
V
IDDQ
Quiescent Supply Current
–
10
15
mA
IDDA
PLL Supply Current
VDD only
15
20
mA
IDD
Dynamic Supply Current
QA and QB @ 60 MHz, QC @ 120 MHz, CL = 30 pF
225
mA
QA and QB @ 25 MHz, QC @ 50 MHz, CL = 30pF
125
CIN
Input Pin Capacitance
–
4-
pF
Notes:
5.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6.
Inputs have pull-up/pull-down resistors that effect input current.
7.
Driving series or parallel terminated 50
Ω (or 50Ω to V
DD/2) transmission lines.
AC Parameters VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C
[8]
Parameter
Description
Conditions
Min
Typ
Max
Unit
Tr / Tf
TCLK Input Rise/Fall
3.0
ns
Fref
Reference Input Frequency
Note 9
Note 9
MHz
Fxtal
Crystal Oscillator Frequency
see Table 3
10
25
MHz
FrefDC
Reference Input Duty Cycle
25
75
%
Fvco
PLL VCO Lock Range
200
480
MHz
Tlock
Maximum PLL Lock Time
10
ms
Tr / Tf
Output Clocks Rise / Fall Time[10]
0.8V to 2.0V
0.15
1.2
ns
Fout
Maximum Output Frequency
Q (
÷2)
-
125
MHz
Q (
÷4)
120
Q (
÷6)
80
Q (
÷8)
60
FoutDC
Output Duty Cycle[10]
TCYCLE/2 – 750
TCYCLE/2 + 750
ps
tpZL, tpZH
Output Enable Time[10](all outputs)
2
10
ns
tpLZ, tpHZ
Output Disable Time[10](all outputs)
2
8
ns
TCCJ
Cycle to Cycle Jitter[10](peak to peak)
± 100
ps
TSKEW
Any Output to Any Output Skew[10,11]
250
350
ps
Tpd
Propagation Delay[11,12]
TCLK0
QFB = (
÷8)
–270
130
530
ps
TCLK1
–330
70
470
Notes:
8.
Parameters are guaranteed by design and characterization. Not 100% tested in production.
9.
Maximum and minimum input reference is limited by VC0 lock range.
10. Outputs loaded with 30 pF each.
11.
50W transmission line terminated into VDD/2.
12. Tpd is specified for a 50 MHz input reference. Tpd does not include jitter.
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