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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DLP650LE датащи(PDF) 13 Page - Texas Instruments |
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DLP650LE датащи(HTML) 13 Page - Texas Instruments |
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13 / 38 page  fSCPCLK = 1 / tC SCPCLK falling–edge capture for SCPDI. SCPDI SCPDO tSCP_PD 50% tSCP_DS tSCP_DH SCPCLK SCPENZ tSCP_NEG_ENZ 50% 50% 50% 50% tSCP_POS_ENZ 50% 50% 50% 50% DI DO tC SCPCLK rising–edge launch for SCPDO. 13 DLP650LE www.ti.com DLPS095 – NOVEMBER 2017 Product Folder Links: DLP650LE Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 6.8 Timing Requirements Over Recommended Operating Conditions (unless otherwise noted). PARAMETER DESCRIPTION SIGNAL MIN TYP MAX UNIT LVDS tC Clock Cycle Duration for DCLK_A LVDS 3.03 ns tC Clock Cycle Duration for DCLK_B LVDS 3.03 tW Pulse Duration for DCLK_A LVDS 1.36 1.52 tW Pulse Duration for DCLK_B LVDS 1.36 1.52 tSU Setup Time for D_A(15:0) before DCLK_A LVDS 0.35 tSU Setup Time for D_A(15:0) before DCLK_B LVDS 0.35 tSU Setup Time for SCTRL_A before DCLK_A LVDS 0.35 tSU Setup Time for SCTRL_B before DCLK_B LVDS 0.35 tH Hold time for D_A(15:0) after DCLK_A LVDS 0.35 tH Hold time for D_B(15:0) after DCLK_B LVDS 0.35 tH Setup Time for SCTRL_A after DCLK_A LVDS 0.35 tH Setup Time for SCTRL_B after DCLK_B LVDS 0.35 tSKEW Channel B relative to Channel A LVDS –1.51 1.51 Figure 2. SCP Timing Requirements See Recommended Operating Conditions for fSCPCLK, tSCP_DS, tSCP_DH, and tSCP_PD specifications. See Recommended Operating Conditions for tr and tf specifications and conditions. |
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