MRF89XA datasheet(40/140 Pages) MICROCHIP

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MRF89XA

DS70000622D-page 40

Preliminary

 2010-2017 Microchip Technology Inc.

2.15.2

FIFO TRANSMIT PLL AND RSSI INTERRUPT REQUEST CONFIGURATION REGISTER

DETAILS

FTPRIREG: FIFO TRANSMIT PLL AND RSSI INTERRUPT REQUEST

CONFIGURATION REGISTER (ADDRESS:0x0E) (POR:0x01)

R/W-0

R/W-1

FIFOFM

FIFOFSC

TXDONE

IRQ0TXST

ENRIRQS

RIRQS

LSTSPLL

LENPLL

bit 7

bit 0

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

r = Reserved

bit 7

FIFOFM: FIFO Filling Method bits

This bit decides the method of filling the FIFO (supports Buffered mode only).

1 = Manually controlled by FIFO fill

0 = Automatically starts when a Sync Word is detected (default)

bit 6

FIFOFSC: FIFO Filling Status or Control bits

This bit indicates the status of FIFO filling and also controls the filling up of the FIFO

(supports Buffered mode only).

STATUS: Reading (FIFOFM = 0)

1 = FIFO getting filled ( Sync Word has been detected)

0 = FIFO filling completed/stopped

CONTROL: Writing (FIFOFM = 1), clears the bit and waits for a new Sync Word (FOVRCLR = 0)

1 = Start filling the FIFO

0 = Stop filling the FIFO

bit 5

TXDONE: Transmit Done bit

This bit selects TXDONE as the corresponding IRQ source.

1 = TXDONE (goes high when the last bit has left the shift register)

0 = TX still in process

bit 4

IRQ0TXST: Transmit Start with IRQ0 bit

This bit indicates transmit start condition with IRQ0 as source.

If DMODE1:DMODE0 = 01  Buffered Mode:

1 = Transmit starts if FIFO is not empty, IRQ0 mapped to FIFOEMPTY

0 = Transmit starts if FIFO is full, IRQ0 mapped to FIFOEMPTY (default)

If DMODE1:DMODE0 = 1x  Packet Mode:

1 = Transmit starts if FIFO is not empty, IRQ0 mapped to FIFOEMPTY

0 = Start transmission when the number of bytes in the FIFO is greater than or equal to the threshold

set by the FTINT<5:0> bits (FIFOCREG<5:0), IRQ0 mapped to FIFO_THRESHOLD

bit 3

ENRIRQS: Enables RSSI IRQ source

1 = Set bit to ‘1’ (Required. It can be enabled at any time, and the user can choose to map this interrupt

to IRQ0/IRQ1 or not.)

0 = Reserved (Default. Setting this bit to ‘0’ disables the RSSI IRQ source.)

bit 2

RIRQS: RSSI IRQ Source

This bit indicates IRQ source as RSSI.

1 = Detected signal is above the value determined by the RTIVAL<7:0> bits (RSTHIREG<7:0>).

0 = Detected signal is less than the value determined by the RTIVAL<7:0> bits (RSTHIREG<7:0>).

Writing a ‘1’ for this bit clears RIRQS.

bit 1

LSTSPLL: Lock Status of PLL bit

1 = PLL locked (lock detected)

0 = PLL not locked

Writing a ‘1’ for this bit clears LSTSPLL.

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