9

ATSAM2193/ATSAM2193-G

2695A–DRMSD–06/03

Reset and Power-

down

During power-up, the RESET input should be held low until the crystal oscillator and

PLL are stabilized. This takes about 20 ms. A typical RC/diode power-up network can

be used.

After RESET, the ATSAM2193 or ATSAM2193-G enters an initialization routine. It takes

around 50 ms before a MIDI IN or MPU message can be processed.

If PDWN is asserted low, then the crystal oscillator and PLL are stopped. The chip

enters a deep power-down sleep mode. To exit power down, PDWN must be asserted

high, then RESET applied.

Power-down mode is managed by an internal power switch. The equivalent schematic

and standard connection is shown in Figure 7.

All the VC2 pins must be connected to PWROUT.

Figure 7. Schematic

Note:

High level for PDWN is VC2 = 2.5V ±10%.

Figure 8. PDWN Connection Example

VC2 Source from

Power Supply

ATSAM2193

ATSAM2193-G

VC2

VC2

VC2

VC2

VC2

VC2

PDWN = L: Power-down Mode (Internal Power Switch Open)

PDWN = H: Operating Mode (Internal Power Switch Closed)

ATSAM2193

ATSAM2193-G

VC2

HOST

PDWN

Control

(High level = 3.3V)

VC3

3.3V

10 kOhm

PDWN

VC3

3.3V

PWRIN

2.5V

PWROUT