TSB41BA3 datasheet(17/63 Pages) TI

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TSB41BA3

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS155A − MAY 2003 − REVISED OCTOBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

tsu

D, CTL, LREQ

xCLK

Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

D, CTL

xCLK

Figure 3. Dx and CTLx Output Delay Relative to xCLK Waveforms

APPLICATION INFORMATION

Please obtain from the TI website or your local TI representative the reference schematics, reference layouts,

debug documents, and software recommendations for the TSB41BA3.

internal register configuration

There are 16 accessible internal registers in the TSB41BA3. The configuration of the registers at addresses 0h

through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the

paged registers) is dependent upon which 1 of 8 pages, numbered 0h through 7h, is currently selected. The

selected page is set in base register 7h. Note that while this register set is compatible with 1394a-2000 register

sets, some fields have been redefined and this register set contains additional fields.

Table 2 shows the configuration of the base registers, and Table 3 gives the corresponding field descriptions.

The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables)

is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

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