AD7729

–12–

REV. 0

Figure 18 shows a flow diagram for calibration of the receive

section.

RxDELAY1

10

CONNECT ADC INPUTS

SHORT ADC INPUTS

RxDELAY1

RxON

0

1

10

RxDELAY2

RESETS TO ZERO

CAN HAVE A VALUE

OF 0...255

48 MCLKs

COUNTER RESETS TO 36

(36

48 MCLKs) TO ALLOW

FOR FILTER SETTLING TIME

40

48 MCLK

RxREADY

RESETS TO ZERO. CAN HAVE A

VALUE OF 0...255

48 MCLKs

RxAUTOCAL

RxEXTCAL

Figure 18. Receive Offset Adjust

Auxiliary Control Functions

The AD7729 also contains an auxiliary DAC that may be used

for AGC. This 10-bit DAC consists of high impedance current

sources, designed to operate at very low currents while main-

taining its dc accuracy. The DAC is buffered by an output am-

plifier and allows a load of 10 k

Ω.

The DAC has a specified output range of 2

× V

×

× DAC/1023

where DAC is the 10-bit digital word loaded into the DAC

register.

To perform a conversion, the DAC is first powered up using the

AUXDACON bit in control register ACRA. After power-up,

10

µs are required for the AUXDAC circuitry to settle. The

AUXDAC is loaded by writing to register AUXDAC. When

the AUXDAC is in power-down mode, the AUXDAC register

will retain its contents. When the AUXDAC is reset, the

AUXDAC register will be set to all zeroes, leading to a voltage

of 2

× V

Voltage Reference

The reference of the AD7729, REFCAP, is a bandgap reference

which provides a low noise, temperature compensated reference

to the IQ receive ADCs and the AUXDAC. The reference is

also made available on the REFOUT pin. The reference has a

value of 1.3 V nominal.

When the AD7729 is powered down, the reference can also be

powered down. Alternatively, by setting bit LP to 1, the refer-

ence remains powered up. This is useful as the power-up time

for the receive section and auxiliary converter is reduced since

the reference does not require time to power up and settle.

Baseband and Auxiliary Serial Ports (BSPORT and ASPORT)

Both the baseband and auxiliary SPORTs are DSP compatible

serial ports which provide access to the 27 on-chip registers as

illustrated in Table IV.

Since some registers are accessible over both the auxiliary and

baseband SPORTs, the user can decide which registers will be

accessible over which SPORT, this feature providing maximum

flexibility for the system designer. The user also has the ability

to adjust the frequency of the SCLKs in each SPORT, which is

useful for power dissipation minimization. Furthermore, it is

possible for the user to access all the ADC and AUXDAC con-

trol registers over one SPORT, the other SPORT being disabled

by tying its serial port enable (SE) low. This feature is useful

when the user has only one SPORT available for communica-

tion with the AD7729.

Resetting the AD7729

The pin RESETB resets all the control registers. All registers

except ASCLKRATE and BSCLKRATE are reset to zero. On

reset, ASCLKRATE and BSCLKRATE are set to 4 so that the

frequency of ASCLK and BSCLK is MCLK/8. As well as reset-

ting the control registers using the reset pin, these registers can

be reset using the reset bits in the baseband and auxiliary regis-

ters. All the auxiliary registers can be reset by taking the bit

ARESET in control register ACRB high. The baseband registers

can be reset by taking bit BRESET in baseband control register

BCRA high. This is illustrated in Table IV. After resetting, the

bits ARESET and BRESET will reset to zero. A reset using

ARESET or BRESET requires 4 MCLK cycles. The registers

ARDADDR, BRDADDR, ASCLKRATE, and BSCLKRATE

can only be reset using the reset pin RESETB—these registers

cannot be reset using the above mentioned bits. A system reset

(using BRESET) requires eight MCLK cycles.

The functions of the control register bits are summarized in

Table IV to Table X.