STV3550 datasheet(105/144 Pages) STMICROELECTRONICS

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STV3550

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Note:

The SSCMS bit is automatically cleared to 0 (slave mode) if the device loses arbitration in a multi-

master environment.

7.7.13 Error Detection

A number of different error conditions can be detected by the SSC2. These are related to the mode

of operation (master or slave, or both).

On detection of any of these error conditions a status flag will be set in the status register,

SSCSTAT. Also, if the relevant enable bit is set in the interrupt enables register, SSCIEN, then an

error interrupt will be generated from the SSC2.

The different error conditions are described below.

Transmit Error

A transmit error can only be generated in slave mode. It indicates that a transfer has been initiated

by a remote master device BEFORE a new transmit data buffer value has been written in to the

SSC2.

In other words the error occurs when old transmit data is going to be transmitted from the slave.

This could cause data corruption in the half-duplex open drain configuration.

The error condition is indicated by the setting of the SSCTE bit in the status register. An interrupt will

be generated if the SSCTEEN bit is set in the interrupt enables register.

The transmit error status bit (and the interrupt, if enabled) is cleared by the next write to the transmit

buffer.

Receive Error

A receive error can be generated in both master and slave modes. It indicates that a new data

frame has been completely received into the shift register and has been loaded into the receive

buffer BEFORE the existing receive buffer contents have been read out.

Consequently, the receive buffer has been overwritten with new data and the old data is lost.

The error condition is indicated by the setting of the SSCRE bit in the status register. An interrupt

will be generated if the SSCREEN bit is set in the interrupt enables register.

The receive error status bit (and the interrupt, if enabled) is cleared by the next read from the

receive buffer.

Phase Error

A phase error can be generated in master and slave modes. It indicates that the data received at

the incoming data pin has changed during the time from one sample before the latching clock edge

and two samples after the edge.

The data at the incoming data pin is supposed to be stable around the time of the latching clock

edge, hence the error condition.

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