DESCRIPTION:
The IDT72T7285/72T7295/72T72105/72T72115 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x72/x36/x18 data flow. These FIFOs offer several key user benefits:
• Flexible x72/x36/x18 Bus-Matching on both read and write ports
• A user selectable MARK location for retransmit
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronous translation on the read or write ports
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 9 Mbit

FEATURES:
• Choose among the following memory organizations:
IDT72T7285 ⎯ 16,384 x 72
IDT72T7295 ⎯ 32,768 x 72
IDT72T72105 ⎯ 65,536 x 72
IDT72T72115 ⎯ 131,072 x 72
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost Empty and Almost-Full flags
• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing