FEATURES
• Single-chip, 1-port, full-duplex or half-duplex, 10/100BaseT switching device
   for low-cost unmanaged and managed
   networks.
• On-chip SmartPath 50 MHz RISC
   CPU core, multi-channel DMA
   controller, MAC-layer interface logic,
   FIFOs, PCI-based expansion port, and
   a flexible memory controller.
• CPU supports background applications
   running on local OS (e.g., SNMP), and
   real-time data-oriented applications
   (e.g., packet forwarding and filtering
   decisions).
• Performs packet switching at a rate of
   200 Mbit/s (full-duplex) or 100 Mbit/s
   (half-duplex).
• Fully compatible with the PM3350
   8-port 10 Mbit/s switch device; may be
   used to create a compact and
   inexpensive mixed 10/100 Mbit/s
   switching hub.
• Filtering and switching at wire rates (up
   to 148,8000 packets per second),
   supporting a mix of Ethernet and
   IEEE 802.3 protocols.
• Expansion port supports a peak
   system bandwidth of 1 Gbit/s, and is
   compatible with industry-standard PCI
   bus (version 2.1).
• Performs all address learning, address
   table management, and aging
   functions for up to 32,768 MAC
   addresses (limited by external
   memory). Address learning rate of up
   to 10,000 addresses per second.
• Maximum broadcast/multicast at wire
   rates with configurable broadcast
   storm rate limiting.
• Low-latency operation in both unicast
   and broadcast modes.
• Configuration, management, MIB
   statistics, and diagnostics available inband.
• Store-and-forward operation with full
   error checking and filtering.
• Flow control supported for both fullduplex and half-duplex operation;
   supports IEEE 802.3x PAUSE frame
   flow control in full-duplex mode, and
   supports user-enabled backpressure
   flow control in half-duplex mode.
• Maintains and collects per-port and
   per-host statistics at wire rates.
• Interfaces directly to industry-standard
   100 Mbit/s transceivers with no glue
   logic via the built-in Medium
   Independent Interface (MII) port with
   full support for the autonegotiation
   function implemented by the PHY
   devices.
• Fully static CMOS operation at 50 MHz
   clock rates.
• Implemented with a 3.3 V core and a
   5 V-compatible I/O.
• Available in a 208-pin PQFP package.