ARCHITECTURAL OVERVIEW
The 82430 PCIset consists of the 82434LX PCMC and 82433LX LBX components plus either a PCI/ISA bridge or a PCI/EISA bridge. The 82430NX PCIset consists of the 82434NX PCMC and 82433NX LBX components plus either a PCI/ISA bridge or a PCI/EISA bridge. The PCMC and LBX provide the core cache and main memory architecture and serves as the Host/PCI bridge. An overview of the PCMC follows the system overview section.

■ Supports the Full 64-bit PentiumÉ Processor Data Bus at Frequencies up to 66 MHz (82433LX and 82433NX)
■ Drives 3.3V Signal Levels on the CPU Data and Address Buses (82433NX)
■ Provides a 64-Bit Interface to DRAM and a 32-Bit Interface to PCI
■ Five Integrated Write Posting and Read Prefetch Buffers Increase CPU and PCI Performance
    — CPU-to-Memory Posted Write Buffer 4 Qwords Deep
    — PCI-to-Memory Posted Write Buffer Two Buffers, 4 Dwords Each
    — PCI-to-Memory Read Prefetch Buffer 4 Qwords Deep
    — CPU-to-PCI Posted Write Buffer 4 Dwords Deep
    — CPU-to-PCI Read Prefetch Buffer 4 Dwords Deep
■ CPU-to-Memory and CPU-to-PCI Write Posting Buffers Accelerate Write Performance
■ Dual-Port Architecture Allows Concurrent Operations on the Host and PCI Buses
■ Operates Synchronously to the CPU and PCI Clocks
■ Supports Burst Read and Writes of Memory from the Host and PCI Buses
■ Sequential CPU Writes to PCI Converted to Zero Wait-State PCI Bursts with Optional TRDYÝ Connection
■ Byte Parity Support for the Host and Memory Buses
    — Optional Parity Generation for Host to Memory Transfers
    — Optional Parity Checking for the Secondary Cache
    — Parity Checking for Host and PCI Memory Reads
    — Parity Generation for PCI to Memory Writes
■ 160-Pin QFP Package