General Description
The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM.

Features
● Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
● Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2”
● Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
● No External RC Network Required
● External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input
● Separate Output Enable for Each Output Bank
● Operates at 3.3 V Vcc
● 125 MHz Maximum Frequency
● On-chip Series Damping Resistors
● Support Spread Spectrum Clock(SSC) Synthesizers
● ESD Protection Exceeds 3000 V per MIL-STD- 883, Method 3015 ; Exceeds 350 V Using Machine Model ( C = 200 pF, R = 0 )
● Latch-Up Performance Exceeds 400 mA per JESD 17
● Packaged in Plastic 24-Pin Thin Shrink SmallOutline Package