The MPC2105A/B and the MPC2106A/B are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications.

• PowerPC–style Burst Counter on Chip
• Flow–Through Data I/O
• Plug and Pin Compatibility
• Multiple Clock Pins for Reduced Loading
• 20 Ω Series Resistors on DL and DH Pins for Noise Reduction (MPC2105A/6A)
• All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rates: Up to 66 MHz
• Fast SRAM Access Times: 10 ns for Tag RAM Match 9 ns for Data RAM
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
• 178 Pin Card Edge Module
• Burndy Connector, Part Number: ELF178KSC–3Z50