Low power consumption technology
 VDD = single power supply voltage of 2.4 to 5.5 V
 HALT mode
 STOP mode
RL78 CPU core
 CISC architecture with 3-stage pipeline
 Minimum instruction execution time: Can be changed
from high speed (0.0625 μs: @ 16 MHz operation
with high-speed on-chip oscillator) to ultra-low speed
(30.5 μs: @ 32.768 kHz operation with subsystem clock)
 Address space: 1 MB
 General-purpose registers: (8-bit register × 8) × 4 banks
 On-chip RAM: 2 KB
Code flash memory
 Code flash memory: 16 to 32 KB
 Block size: 1 KB
 Only write after erase is possible
 On-chip debug function
 Self-programming (with no boot swap function/flash shield window function)
Data flash memory