▪ 2 configurable low drift I2O delays up to 2.9ns; maintain
transport delay for various topologies
▪ LP-HCSL outputs; eliminate 24 resistors (9ZML1232E)
▪ LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors
(9ZML1252E)
▪ 9 selectable SMBus addresses; multiple devices can share
same SMBus segment
▪ Separate VDDIO for outputs; allows maximum power savings
▪ PLL or Bypass Mode; PLL can dejitter incoming clock
▪ Hardware or software-selectable PLL BW; minimizes jitter
peaking in downstream PLLs
▪ Spread spectrum compatible; tracks spreading input clock for
EMI reduction
▪ SMBus interface; software can modify device settings without
hardware changes
▪ 10 × 10 mm 72-VFQFPN package; small board footprint