1FEATURES
• Dual 1:6 Differential Buffer
• Low Additive Jitter: <300 fs rms
in 10 kHz – 20 MHz
• Low Within Bank Output Skew of 45 ps (Max)
• Universal Inputs Accept LVDS, LVPECL,
LVCMOS
• One Input Dedicated for Six Outputs
• Total of 12 LVDS Outputs, ANSI EIA/TIA-644A
Standard Compatible
• Clock Frequency up to 800 MHz
• 2.375–2.625 V Device Power Supply
• LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
• Industrial Temperature Range –40°C to 85°C
• Packaged in 6 mm x 6 mm 40-pin QFN (RHA)
• ESD Protection Exceeds 3-kV HBM, 1-kV CDM

APPLICATIONS
• Telecommunications/Networking
• Medical Imaging
• Test and Measurement Equipment
• Wireless Communications
• General Purpose Clocking

DESCRIPTION
The CDCLVD2106 clock buffer distributes two clock
inputs (IN0, IN1) to a total of 12 pairs of differential
LVDS clock outputs (OUT0, OUT11). Each buffer
block consists of one input and 6 LVDS outputs. The
inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD2106 is specifically designed for driving
50-Ω transmission lines. In case of driving the inputs
in single ended mode, the appropriate bias voltage
(VAC_REF) should be applied to the unused negative
input pin.
Using the control pin (EN), outputs can be either
disabled or enabled. If the EN pin is left open two
buffers with all outputs are enabled, if switched to a
logical "0" both buffers with all outputs are disabled
(static logical "0"), if switched to a logical "1", one
buffer with six outputs is disabled and another buffer
with six outputs is enabled. The part supports a fail
safe function. It incorporates an input hysteresis,
which prevents random oscillation of the outputs in
absence of an input signal.
The device operates in 2.5V supply environment and
is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD2106 is packaged in
small 40-pin, 6-mm × 6-mm QFN package.