1 Features
1• Differential Analog Inputs
• Total Output Power at 10%THD+N
– 60-W Stereo Continuous into 8 Ω in BTL
Configuration at 30 V
– 110-W Stereo Peak into 4 Ω in BTL
Configuration at 30 V
• Total Output Power at 1%THD+N
– 50-W Stereo Continuous into 8 Ω in BTL
Configuration at 30 V
– 90-W Stereo Peak into 4 Ω in BTL
Configuration at 30 V
• Advanced Integrated Feedback Design with Highspeed
Gate Driver Error Correction
(PurePath™ Ultra-HD)
– Signal Bandwidth up to 100 kHz for High
Frequency Content From HD Sources
– Ultra Low 0.005% THD+N at 1 W into 4 Ω and
<0.01% THD+N to Clipping
– 60 dB PSRR (BTL, No Input Signal)
– <55 μV (A-Weighted) Output Noise
– >110 dB (A Weighted) SNR
• Multiple Configurations Possible:
– Stereo, Mono, 2.1 and 4xSE
• Click and Pop Free Startup and Stop
• 94% Efficient Class-D Operation (8 Ω)
• Wide 12-V to 30-V Supply Voltage Operation
• Self-Protection Design (Including Undervoltage,
Overtemperature, Clipping, and Short Circuit
Protection) With Error Reporting
• EMI Compliant When Used With Recommended
System Design

2 Applications
• High End Soundbar
• Mini Combo Systems
• Blu-Ray Disc™ / DVD Receivers
• Active Speakers

3 Description
The TPA3244 device is a high performance Class-D
power amplifier that enables true premium sound
quality with Class-D efficiency. It features an
advanced integrated feedback design and proprietary
high-speed gate driver error correction (PurePath™
Ultra-HD). This technology allows ultra low distortion
across the audio band and superior audio quality.
With a 30-V power supply the device can drive up to
2 x 110 W peak into 4-Ω load and 2 x 60 W
continuous into 8-Ω load and features a 2-VRMS
analog input interface that works seamlessly with high
performance DACs such as Burr-Brown PCM52xx
DAC Family from TI (that is, PCM5242 / PCM5252).
In addition to excellent audio performance, TPA3244
achieves both high power efficiency and very low
power stage idle losses below 0.45 W. This is
achieved through the use of 65 mΩ MOSFETs and
an optimized gate driver scheme that achieves
significantly lower idle losses than typical discrete
implementations.