1FEATURES
2• Single +3.3V Supply Operation
• Internal Sample-and-Hold
• Internal Reference
• Outputs 2.4V to 3.6V Compatible
• Power Down Mode
• Duty Cycle Stabilizer
• Multiplexed Output Mode

KEY SPECIFICATIONS
• Resolution 10 Bits
• DNL ±0.16 LSB (typ)
• SNR (fIN = 10 MHz) 61 dB (typ)
• SFDR (fIN = 10 MHz) 85 dB (typ)
• Data Latency 7 Clock Cycles
• Power Consumption
– Operating 370 mW (typ)
– Power Down Mode 36 mW (typ)

APPLICATIONS
• Ultrasound and Imaging
• Instrumentation
• Communications Receivers
• Sonar/Radar
• xDSL
• DSP Front Ends

DESCRIPTION
The ADC10DL065 is a dual, low power monolithic
CMOS analog-to-digital converter capable of
converting analog input signals into 10-bit digital
words at 65 Megasamples per second (MSPS). This
converter uses a differential, pipeline architecture with
digital error correction and an on-chip sample-and- hold circuit to minimize power consumption while
providing excellent dynamic performance and a 250
MHz Full Power Bandwidth. Operating on a single
+3.3V power supply, the ADC10DL065 achieves 9.8
effective bits at nyquist and consumes just 370 mW
at 65 MSPS, including the reference current. The
Power Down feature reduces power consumption to
36 mW.
The differential inputs provide a full scale differential
input swing equal to 2 times VREF with the possibility
of a single-ended input. Full use of the differential
input is recommended for optimum performance. The
digital outputs from the two ADC's are available on a
single multiplexed 10-bit bus or on separate buses.
Duty cycle stabilization and output data format are
selectable using a quad state function pin. The output
data can be set for offset binary or two's complement.
To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC10DL065
can be connected to a separate supply voltage in the
range of 2.4V to the analog supply voltage. This
device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of
−40°C to +85°C. An evaluation board is available to
ease the evaluation process.