Qualified for Automotive Applications
ESD Protection Exceeds 1500 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
Typical tpd = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion

description/ordering information
The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH)
output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled
by a low level at the shift/load (SH/LD) input. The SN74HC165 also features a clock-inhibit (CLK INH) function
and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.