Use CDCVF2509A as a Replacement for
this Device
Designed to Meet PC SDRAM Registered
DIMM Specification
Spread Spectrum Clock Compatible
Operating Frequency 25 MHz to 125 MHz
Phase Error Time Minus Jitter at 66 MHz to
100 MHz Is ±150 ps
Jitter (peak − peak) at 66 MHz to 100 MHz Is
±80 ps
Jitter (cycle − cycle) at 66 MHz to 100 MHz
Is |100 ps|
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
Separate Output Enable for Each Output
Bank
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V

description
The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock drivers. They use a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
They are specifically designed for use with synchronous DRAMs. The CDC2509B operates at 3.3-V VCC. They
also provide integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2509B does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2509B requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.