Low rDS(on) . . . 1 Ω Typ
Output Short-Circuit Protection
Avalanche Energy . . . 75 mJ
Eight 350-mA DMOS Outputs
50-V Switching Capability
Four Distinct Function Modes
Low Power Consumption

description
This power logic 8-bit addressable latch controls
open-drain DMOS-transistor outputs and is
designed for general-purpose storage applications
in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multifunctional
device capable of operating as eight
addressable latches or an 8-line demultiplexer
with active-low DMOS outputs. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS-transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G should be held high (inactive) while the
address lines are changing. In the 8-line
demultiplexing mode, the addressed output is
inverted with respect to the D input and all other
outputs are high. In the clear mode, all outputs are
high and unaffected by the address and data
inputs.
Separate power ground (PGND) and logic ground
(LGND) terminals are provided to facilitate
maximum system flexibility. All PGND terminals
are internally connected, and each PGND
terminal must be externally connected to the
power system ground in order to minimize
parasitic impedance. A single-point connection
between LGND and PGND must be made
externally in a manner that reduces crosstalk
between the logic and load circuits.