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TMPE627-DOC датащи (PDF) - TEWS Technologies GmbH

TMPE627-DOC Datasheet PDF - TEWS Technologies GmbH
номер детали TMPE627-DOC
скачать  TMPE627-DOC скачать
объем файла   395.32 Kbytes
Page   3 Pages
производитель  TEWS [TEWS Technologies GmbH]
домашняя страница  https://www.tews.com/
Logo TEWS - TEWS Technologies GmbH
подробное описание детали Reconfigurable FPGA with AD/DA & Digital I/O PCIe Mini Card

TMPE627-DOC Datasheet (PDF)

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TMPE627-DOC Datasheet PDF - TEWS Technologies GmbH

номер детали TMPE627-DOC
скачать  TMPE627-DOC Click to download

объем файла   395.32 Kbytes
Page   3 Pages
производитель  TEWS [TEWS Technologies GmbH]
домашняя страница  https://www.tews.com/
Logo TEWS - TEWS Technologies GmbH
подробное описание детали Reconfigurable FPGA with AD/DA & Digital I/O PCIe Mini Card

TMPE627-DOC датащи (HTML) - TEWS Technologies GmbH


TMPE627-DOC Информация о продукте

Application Information
The TMPE627 is a standard full PCI Express Mini Card,
providing a user programmable Xilinx Artix-7 7A50T
FPGA.
The TMPE627 provides 14 ESD-protected 5 V-tolerant
TTL lines. All I/O lines are individually programmable as
input or output. TTL I/O lines can be set to high, low, or
tristate. Each TTL I/O line has a pull-resistor to a common
programmable pull-up voltage that can be set so +3.3 V,
+5 V and GND.
The 16 bit ADC offers 4 input channels that can be
operated in single-ended or differential mode. It offers
software selectable input voltage ranges of 0-5.12 V, 0-
10 V, 0-10.24 V, ±5 V, ±5.12 V, ±10 V and ±10.24 V with a
sampling rate of up to 200 ksps.
The DAC offers 4 channels of 16 bit analog outputs with
software selectable output voltage ranges of 0-5 V, 0-
10 V, 0-10.8 V, ±5 V, ±10 V or ±10.8 V. The output voltage
range can be individually set per channel. The conversion
time is typ. 10 μs and the DAC outputs are capable to
drive a load of 2 kΩ, with a capacitance up to 4000 pF.
Each TMPE627 is factory calibrated. The calibration
information is stored in an on-board serial EEPROM
unique to each TMPE627 module.
The I/O signals are accessible through a 30 pin Pico-
Clasp latching connector.
The User FPGA is configured by a SPI flash. An in-circuit
debugging option is available via a JTAG header for read
back and real-time debugging of the FPGA design (using
the Vivado ILA). With the TA308 Programming Kit direct
JTAG access to the FPGA is possible, using the Xilinx
Platform Cable USB.
User applications for the TMPE627 with 7A50T FPGA can
be developed using the design software Vivado Design
Suite HL WebPACK Edition, which can be downloaded
free of charge from www.xilinx.com.
TEWS offers a well-documented basic FPGA Example
Application design. It includes a constraints file with all
necessary pin assignments and basic timing constraints.
The example design covers the main functionalities of the
TMPE627. It implements PCIe to register mapping and
basic I/O. It comes as a Xilinx Vivado Design Suite project
with source code and as a ready-to-download bit stream.
The TMPE627 provides a basic heatsink to facilitate
thermal management. The heatsink can be used to install
additional cooling solutions like passive or active heatsinks
or to provide a thermal connection to an enclosure.




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