FEATURES
64× decimation of a stereo pulse density modulation (PDM)
bit stream to pulse code modulation (PCM) audio data
Slave I2S or time division multiplexed (TDM) output interface
Configurable TDM slots
I/O supply operation: 1.62 V to 3.6 V
64× output sample rate PDM clock
64×/128×/192×/256×/384×/512× output sample rate BCLK
Automatic BCLK ratio detection
Output sample rate: 4 kHz to 96 kHz
Automatic PDM CLK drive at 64× the sample rate
Automatic power down with BCLK removal
0.67 mA operating current at 48 kHz and 1.8 V IOVDD supply
Shutdown current: <1 μA
8-ball, 1.56 mm × 0.76 mm, 0.4 mm pitch WLCSP
Power-on reset
APPLICATIONS
Mobile computing
Portable electronics
Consumer electronics