GENERAL DESCRIPTION
The Austin Semiconductor, Inc. Zero Bus Latency SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

FEATURES
• High frequency and 100% bus utilization
• Fast cycle times: 11ns & 12ns
• Single +3.3V +5% power supply (VDD)
• Advanced control logic for minimum control signal interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W (READ/WRITE) control pin
• CKE pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data I/Os and control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to eliminate the need to control OE
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or Interleaved Burst Modes
• Burst feature (optional)
• Pin/function compatibility with 2Mb, 8Mb, and 16Mb ZBL SRAM
• Automatic power-down