GENERAL DESCRIPTION
W6691 consists of one D channel HDLC controller and two B HDLC controller channel access. The HDLC controller facilitates efficient access to signaling, data and voice services. It provides multiplex/non- mutiplexe 8- bit microprocessor interface. The interface is selected by external MBS selection. In addition, W6691 can be operated in TE, LT-S and LT-T mode programmed by external pin. In TE mode, W6691 provides PCM bus or GCI bus to connect with CODEC. In LT mode, it can used in NT2 application.

FEATURES
• Full Duplex 2B+D S/T interface transceiver compliant with ITU I.430 Recommendation
• One D channel HDLC controller
    - Maskable address recognition
    - Transparent (HDLC) mode
    - FIFO buffer (2 * 64)
• Two B channel HDLC controller
    - Maskable address recognition
    - Transparent (HDLC) mode
    - FIFO buffer (2 * 128)
• Various B channel switching capabilities and PCM intercom
• Two PCM CODEC interfaces for speech and POTS application
• GCI interface connects with other peripheral device in TE, LT-S and LT-T mode.
• Multi-frame synchronization
• 8-bits Intel mode or Motorola mode interface accesses B channel and Command/Indication channel.
• The timing clock recovery depends on operating mode.
• DPLL circuit designed in chip for NT2 application.
• Four kind of the extended interrupt trigger mode.
• Two kind of output interrupt polarity selection can be programmed.(Positive level and negative Level)
• Added reset signal to reset other chip.
• Loop back function for testing.
• Layer1 Activate Indication Output can be connected to LED
• Two of programmable timer
• 3.3 Volt power supply
• 3.3 Volt output; Maximum Input is 5.0Volt
• Advanced CMOS technology
• 64 pin LQFP or 68 pin PLCC package