1. General description
The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs,
common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn
outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requirements
on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.
When LOW, MR resets all flip-flops (Qn = LOW, Qn = HIGH), independent of CP and Dn. Inputs
include clamp diodes. This enables the use of current limiting resistors to interface inputs to
voltages in excess of VDD.
2. Features and benefits
• Wide supply voltage range from 3.0 V to 15.0 V
• CMOS low power dissipation
• High noise immunity
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-B exceeds 200 V
• Specified from -40 °C to +85°C and from -40 °C to +125 °C
3. Applications
• Shift registers
• Buffer/storage register
• Pattern generator