Features
• Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
• Two selectable differential CLKx, nCLKx inputs
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following
input levels: LVDS, LVPECL, LVHSTL, HCSL
• Maximum output frequency: 100MHz
• Translates any single ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
• Synchronous clock enable
• Additive phase jitter, RMS: 0.21ps (typical)
• Output skew: 200ps (maximum)
• Part-to-part skew: 900ps (maximum)
• Bank skew: 180ps (maximum)
• Propagation delay: 5ns (maximum)
• Output supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
• -40°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package