Features
• Supports category 5 cables and above with attenuation in
excess of 24dB at 100 MHz.
• Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sub layers functions of IEEE
standard.
• 10Base-T and 100Base-TX IEEE 8802.3 compliant
• MIIM (MDC/MDIO) management bus for PHY register
configuration
• RMII interface support with external 50 MHz system clock
• Single 3.3V power supply
• Highly configurable, supports:
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full and half-duplex modes
• Auto-MDI/MDIX crossover correction
• Low-power CMOS (typically 300 mW)
• Power-Down mode (typically 21mW)
• Programmable LEDs
• Interrupt output pin
• Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander
correction
– Transmit wave shaping and stream cipher
scrambler
– MLT-3 encoder and NRZ/NRZI encoder
• Core power supply (3.3 V)
• 3.3 V/1.8 V VDDIO operation supported
• Smart power control with deep power down feature
• Available in 40-pin (6mm x 6mm) QFN package, Pb-free
• Industrial Temp and Lead Free