FEATURES
HIGHLIGHTS
• Single PLL chip:
• Features 0.5 mHz to 560 Hz bandwidth
• Provides node clock for ITU-T G.8261/G.8262 Synchronous
Ethernet (SyncE)
• Exceeds GR-253-CORE and ITU-T G.813 jitter generation
requirements
• Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially
for Japan TCM-ISDN network timing based ADSL equipments
• Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applications
MAIN FEATURES
• Provides an integrated single-chip solution for Synchronous Equipment
Timing Source, including Stratum 3, Stratum 4E, Stratum 4,
SMC, EEC-Option 1 and EEC-Option 2 Clocks
• Provides 156.25 MHz clock for 10 Gig Ethernet Application, with
less than 0.7 ps of RMS Phase Jitter (12 kHz - 20 MHz)
• Employs PLL architecture to feature excellent jitter performance
and minimize the number of the external components
• Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or
locks to T0 DPLL
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine. It supports Free- Run, Locked and Holdover
modes
• Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19
steps) and damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8
ppm instantaneous holdover accuracy
• Supports hitless reference switching to minimize phase transients
on T0 DPLL output to be no more than 0.61 ns
• Supports phase absorption when phase-time changes on T0
selected input clock are greater than a programmable limit over an
interval of less than 0.1 seconds
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Provides OUT1~OUT7 output clock frequencies covering from 2
kHz to 625MHz
• Includes 125 MHz and 156.25 MHz for CMOS outputs
• Includes 125 MHz, 156.25 MHz, 312.5 MHz and 625 MHz for differential
outputs