FEATURES
• Octal Framer supporting T1, E1 and J1 formats
• Provides programmable system interface to support Zarlink Semiconductor
Inc. ST-BUS®, AT&T® CHI and MVIP bus, supporting
data rates of 1.544, 2.048 & 8.192 Mb/s; up to four links can be
byte-interleaved on one system bus without external logic
• Provides up to three internal floating HDLC controllers for each
framer to support ISDN PRI and V5.X interface. Each HDLC contains
128-byte deep FIFOs in both receive and transmit directions
• Provides jitter attenuation performance exceeding the requirements
set by the associated standards for both Rx and Tx path
• Provides payload, line and digital loopbacks
• Provides a floating Pseudo Random Bit Sequence / repetitive pattern
generator/detector, which can be assigned to any one of eight
framers, the pattern may be inserted / detected on an unframed or
Nx64K or Nx56K (T1 only) basis
• Provides signaling insertion / extraction for CCS / CAS and RBS
signaling system
• Provides programmable codes insertion, data / sign inversion and
digital milliwatt code insertion on a per channel / timeslot basis
• Supports automatic / manual alarming transmit and integration
• Provides performance monitor to count CRC error, framing bit error,
far end block CRC error (E1), out of frame event (T1/J1) and
change of frame alignment event (T1/J1)
• Provides programmable Inband Loopback Code transmitter/
receiver, Bit Oriented Message generator/detector
• Supports polled or interrupt driven processing for all events
• Supports multiplexed or non-multiplexed address/data bus MPU
interface for configuration, control and status monitoring
• JTAG boundary scan meets IEEE 1149.1
• Low power 3.3 V CMOS technology with 5 V tolerant inputs
• Operating industrial temperature range: -40 °C to +85 °C
• Package available: 128 pin PQFP
144 pin PBGA
Green Package Option available